Area: | Department of Electrical and Computer Engineering |
Credits: | 25.0 |
Contact Hours: | 3.0 |
Lecture: | 1 x 2 Hours Weekly |
Laboratory: | 1 x 1 Hours Weekly |
Syllabus: | The design process and its management - theory and practice. Hierarchical design. Computer representation of digital systems - schematics and hardware description languages, behavioural description, register transfer logic. Introduction to VHDL. System and sub system simulation. Design verification. Functional testing, test vector generation. Fault simulation and fault grading. Automatic system partitioning and logic synthesis. ASIC design flows. |
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Unit Outcomes: | On successful completion of this unit you will be able to understand a VHDL description of a circuit, create medium scale integrated circuits using VHDL and design functional testing configurations for digital systems. |
Texts and references listed below are for your information only and current as of September 30, 2003. Some units taught offshore are modified at selected locations. Please check with the unit coordinator for up-to-date information and approved offshore variations to unit information before finalising study and textbook purchases. |
Unit References: | No prescribed references. |
Unit Texts: | Rushton, A., 1998, 'VHDL for Logic Synthesis', 2nd edition, Wiley, New York. |
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Unit Assessment Breakdown: | Laboratory Reports 20%. Design Assignment 80%. |
Field of Education: | 31300 Electrical and Electronic Engineering and Technology (Narrow Grouping) | HECS Band (if applicable): | 2 |
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Extent to which this unit or thesis utilises online information: | Informational | Result Type: | Grade/Mark |
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AvailabilityAvailability Information has not been provided by the respective School or Area. Prospective students should contact the School or Area listed above for further information.
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