11338 (v.3) Computer Aided Engineering of Digital Systems 601

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Area:	Department of Electrical and Computer Engineering
Credits:	25.0
Contact Hours:	3.0
Lecture:	1 x 2 Hours Weekly
Laboratory:	1 x 1 Hours Weekly
Syllabus:	The design process and its management - theory and practice. Hierarchical design. Computer representation of digital systems - schematics and hardware description languages, behavioural description, register transfer logic. Introduction to VHDL. System and sub system simulation. Design verification. Functional testing, test vector generation. Fault simulation and fault grading. Automatic system partitioning and logic synthesis. ASIC design flows.
Unit Outcomes:	On successful completion of this unit you will be able to understand a VHDL description of a circuit, create medium scale integrated circuits using VHDL and design functional testing configurations for digital systems.
Text and references listed above are for your information only and current as of September 30, 2003. Please check with the unit coordinator for up-to-date information.
Unit References:	No prescribed references.
Unit Texts:	Rushton, A., 1998, 'VHDL for Logic Synthesis', 2nd edition, Wiley, New York.
Unit Assessment Breakdown:	Laboratory Reports 20%. Design Assignment 80%.