11338 (v.3) Computer Aided Engineering of Digital Systems 601
| Area: | Department of Electrical and Computer Engineering |
| Contact Hours: | 3.0 |
| Credits: | 25.0 |
| Lecture: | 1 x 2 Hours Weekly |
| Laboratory: | 1 x 1 Hours Weekly |
| The design process and its management - theory and practice. Hierarchical design. Computer representation of digital systems - schematics and hardware description languages, behavioural description, register transfer logic. Introduction to VHDL. System and sub system simulation. Design verification. Functional testing, test vector generation. Fault simulation and fault grading. Automatic system partitioning and logic synthesis. ASIC design flows. |
| Year | Location | Period | Internal | Area External | Central External | | 2003 | Bentley Campus | Semester 1 | Y | | | | 2003 | Bentley Campus | Semester 2 | Y | | | |
Current as of: October 30, 2003 13:11:55
CRICOS provider code 00301J
