| Area: |
Department of Electrical and Computer Engineering |
| Credits: |
25.0 |
| Contact Hours: |
3.0 |
| |
| ** The tuition pattern below provides details of the types of classes and their duration. This is to be used as a guide only. For more precise information please check your unit outline. ** |
| |
| Lecture: |
1 x 2 Hours Weekly |
| Laboratory: |
1 x 1 Hours Weekly |
| |
| Syllabus: |
The design process and its management - theory and practice. Hierarchical design. Computer representation of digital systems - schematics and hardware description languages, behavioural description, register transfer logic. Introduction to VHDL. System and sub system simulation. Design verification. Functional testing, test vector generation. Fault simulation and fault grading. Automatic system partitioning and logic synthesis. ASIC design flows. |
| |
| ** To ensure that the most up-to-date information about unit references, texts and outcomes appears, they will be provided in your unit outline prior to commencement. ** |
| |
| Field of Education: | 031305 Computer Engineering |
| Funding Cluster: | 08 - Engineering, Science, Surveying |
| SOLT (Online) Definitions*: | Informational
*Extent to which this unit or thesis utilises online information |
| Result Type: | Grade/Mark |
Availability |
| Availability Information has not been provided by the respective School or Area. Prospective students should contact the School or Area listed above for further information. |
