5507 (v.5) Computer Structures 601
| Area: | Department of Electrical and Computer Engineering |
| Contact Hours: | 4.0 |
| Credits: | 25.0 |
| Lecture: | 1 x 2 Hours Weekly |
| Laboratory: | 1 x 2 Hours Weekly |
| Anti Requisite(s): | 306883 (v.1) Computer Structures 501 or any previous version
|
| The design process for computer structures. Architectural philosophies - RISC and CISC. Processor performance measurement and analysis. Processor organisations. Instruction set - register file interactions. Exploiting instructional level parallelism - pipelining, scheduling VLIW. Models of distributed memory and memory management. Exception handling. System implementation issues - logical, and physical organisation, interconnection busses. Models of distributed memory and memory management. |
| Year | Location | Period | Internal | Area External | Central External | | 2003 | Bentley Campus | Semester 1 | Y | | | | 2003 | Bentley Campus | Semester 2 | Y | | | |
Current as of: August 29, 2003 15:52:10
CRICOS provider code 00301J
