12705 (v.2) Computer Engineering 203

Area:

Department of Electrical and Computer Engineering

Credits:

25.0

Contact Hours:

4.0

Lecture:

1 x 2 Hours Weekly

Tutorial:

1 x 1 Hours Fortnightly

Laboratory:

1 x 3 Hours Fortnightly

Prerequisite(s):

    12702 (v.2) Computer Engineering 103 or any previous version
    OR
    305672 (v.1) Computer Engineering 107 or any previous version

Syllabus:

Combinational Logic Circuit Design, Sequential Circuit Design, Registers and Counters, Memory and Programmable Logic Devices, Datapaths, Control Unit, Algorithm State Machines, Instruction Set Architecture, Input-Output and Communication, Memory Systems, Microcontroller Interfacing Concepts, Parallel Input-Output, Serial Subsystems, Programmable Timer Operations, Analog Converters, Microcontroller Applications.

Unit Outcomes:

On completion of this unit students will be able to understand the principles of registers and counters, memory and programmable logic devices, Register Transfer and Datapaths, the control unit and Instruction Set Architecture. Design and implement memory systems. Understand the principles of interfacing, parallel input/output, serial subsystems, programmable timer and analogue converter of a typical microcontroller. Design and implement hardware and software for control applications using a typical 8-bit microcontroller.

Text and references listed above are for your information only and current as of September 30, 2003. Please check with the unit coordinator for up-to-date information.

Unit References:

Mano, M.M. and Kime, C.R., 2000, 'Logic and Computer Design Fundamentals', 2nd Edition", Prentice-Hall, New York.

Unit Texts:

Spasov, P., 2002, 'Microcontroller Technology The 68HC11', 4 th Edition, Prentice-Hall, New York.

Unit Assessment Breakdown:

Laboratory 20% (Lab Report 1 5%, Lab Report 2 10%, Lab Work Book 5%). Assignments 15% (Assignment 1 5% Assignment 2 10%). Mid Semester Examination 15%. Final Examination 50%. To pass this unit students must obtain a total assessment mark of at least 50%and submit all Laboratory reports and assignments.

Year	Location	Period	Internal	Area External	Central External
2004	Bentley Campus	Semester 1	Y